With the advances in microelectronic technologies, integrated circuits have come to the nanometer era. The feature sizes of the microelectronic devices are getting smaller, and the chip scale is getting larger with millions or even billions of transistors being placed on a single chip. Semiconductor manufacturing process has evolved into 28-nm node or even beyond; when the minimum line width of the chip layout is getting yet smaller and the scale of chip is getting larger, the layout design also becomes more complicated. Even when using the mainstream 193 nm lithographic process, the system-on-a-chip designed in accordance with the design rules may still suffer a low yield of finished products. Therefore, it is important to quantify the influential factors so as to improve the product yield.